The present invention relates to real time correction of digital PWM amplifiers.
It is desirable to produce high quality audio output while directly driving the speaker with a class D output. Class D amplifiers are desirable in audio power amplifiers and the like because they are efficient, and they can handle high power signals. The high efficiency allows for smaller power supplies, and smaller heat sinks. Typically this technique uses a one-bit signal, of two levels, for example +40 Volts and xe2x88x9240 Volts. The one bit signal is filtered through a simple low pass filter and driven into a loudspeaker.
It is further desirable to implement all of the logic to perform the output amplification digitally. Digital logic is inexpensive and dense. A digital input is preferred, because the majority of source signals are digital, in order to take advantage of digital signal processing. One well known technique provides a two level control signal to the Class D drivers via a delta sigma modulator and a pulse wave modulator (PWM). FIG. 1 (prior art) shows a conventional high power digital PWM amplifier. The digital audio input arrives at delta sigma modulator 102, which provides a multilevel noise shaped signal. Modulator 102 feeds PWM 104, which turns the multilevel noise shaped signal into a two level pulse modulated signal. This signal controls drivers 106. Low pass filter 110 removes high frequencies from the output of the switches, and the filtered output 112 drives speakers or other high power load.
The rate at which the output signal switches between levels is typically 200 KHz to 2 MHz for audio applications. The timing of the edges is typically 20 MHz to 200 MHz.
The digital signal is applied to power switches that drive the output filter. In a low power system, these switches can be viewed as equivalent to a high power logic inverter. The fidelity of the switch is nearly perfect. By this it is meant that the rise and fall times are fast, that the on resistance is low relative to the load, and that the off resistance is high. However, in higher power systems, the switch is much less ideal. Time delays, dead time, slew rate, and other characteristics make the switch non-ideal. In addition, the power supply is not perfectly regulated, and not of zero ohm impedance. The imperfections create signal distortion, and increases noise.
References relevant to the present invention include U.S. Pat. No. 5,815,102, by the present inventor, Patent Application Ser. No. 09/510,034, by the present inventor (incorporated herein by reference), xe2x80x9cToward the 24-bit DAC: Novel Noise-Shaping Topologies Incorporating Correction for the Nonlinearity in a PWM OutPut Stagexe2x80x9d by Peter Craven, J. Audio Eng. Soc., Vol. 41, No., 5, May 1993, and U.S. Pat. Nos. 5,548,286 and 5,784,017 by Craven. See also WO 97/37433 by L. Risbo et al.
A need remains in the art for apparatus and methods to reduce the distortion and noise in high power digital PWM amplifiers.
It is an object of the present invention to provide apparatus and methods to reduce the distortion and noise in high power digital PWM amplifiers.
In order to reduce these effects, the difference between the desired switch signal and the actual switch signal is measured on a pulse by pulse basis. This analog error is converted into a digital signal with an analog to digital converter (ADC). The digital error signal is then used to correct the feedback of the delta sigma modulator in real time. Preferably, more than one moment (integral) of the modulator signal is corrected via the feedback. Preferably, the predictable error of the circuitry (which is known a priori) is also corrected by correcting the delta sigma modulator feedback, for example by using the techniques described in U.S. Pat. No. 5,815,102, by the present inventor.
A specialized ADC according to the present invention allows the loop delay to be low, without compromising accuracy.